The present invention relates to non-volatile memory cells with double level of polycrystalline silicon and in particular an electrically erasable non-volatile memory cell (FLASH EEPROM) designed for use in analog computing devices in the charge domain.
Such devices are designed to process input signals in analog form to supply output signals again in analog form and are used in associative memories for pattern recognition systems, in associative memories for correction of digital data transmission errors, in D/A converters and neural networks.
In the prior art said devices are provided by means of digital circuits.
The use of digital circuits however requires converting the analog input signals into digital signals, processing the signals in digital form and reconverting said signals in analog form.
The considerable circuit complexity of said devices is in contrast with the present tendency toward integrating an ever greater number of circuits on the same chip to obtain higher computing powers with low consumption and low power dissipation.
The technical problem underlying the present invention is to make available to those skilled in the art a capacitive element with non-linear characteristic, programmable in analog mode, of very small size, such as to make possible the provision of analog computing devices with very high density occupying a particularly small integration area.
This problem is solved by a non-volatile double-poly memory cell in which the channel region extends laterally, perpendicular to the source-drain direction, into two lateral zones beneath the two gates. This provides more favorable capacitive coupling.
The characteristics and advantages of the device in question are set forth in the description of a preferred embodiment thereof given below by way of nonlimiting example with reference to the annexed drawings.
At least one prior art EPROM design has used a gate shaped like a cross: This structure appears in U.S. Pat. Nos. 4,698,900 and 4,892,840, which are both hereby incorporated by reference. Note that the basic capacitance relations followed by these patents is quite different from that of the present invention, since these patents teach that: "For maximum programming efficiency . . . it is desirable to maintain a large capacitance between the control gate and the floating gate, and a minimum capacitance between the floating gate and the underlying semiconductor substrate . . . . " (U.S. Pat. No. 4,892,840). This is done in order to maximize the voltage between the floating gate and substrate, when the control gate is pulled high. (The series combination of capacitances acts as a voltage divider.)
Additional background on neural networks and analog memory can be found in the following publications, all of which are hereby incorporated by reference: Sin et al., "EEPROM as an analog storage device, with particular applications in neutral networks," 39 IEEE TRANSACTIONS ON ELECTRON DEVICES 1410 (June 1992); Alspector et al., "A neuromorphic VLSI learning system," Proc. 1987 Stanford Conf. on Advanced Research in VLSI 313; A. P. Chandrakasan et al., "Low-Power CMOS Digital Design," 27 IEEE J. Solid State Circuits 473 (1992); O. Fujita and Y. Amemiya, "A Floating-Gate Analog Memory Device for Neural Networks," 40 IEEE Trans. Electron Devices 2029 (1993); M. Holler et al., "An Electrically Trainable Neural Network Chip (ETANN) with 1024 `Floating Gate` Synapses," in Proc. IJCNN, June 1989, pp. 2.191-2.196; J. Lazzaro, J. Wawrzynek, A. Kramer, "Systems Technologies for Silicon Auditory Models", 14 IEEE Micro No.3, pp. 7-15, (June 1994); A. Kramer et al., "EEPROM Device as a Reconfigurable Analog Element for Neural Networks," 1989 IEDM Tech. Dig., paper 10.3; A. Kramer et al., "Compact EEPROM-based Weight Functions," in Neural Information Processing Systems 3 at 1001-1007 (ed. R. P. Lippmann et al. 1991); T. Ong, P. K. Ko, and C. Hu, "The EEPROM as an Analog Memory Device," 36 IEEE Trans. Electron Dev. 1840 (1989); T. Shibata and T. Ohmi, "A Functional MOS Transistor Featuring Gate-Level Weighted Sum Threshold Operations," 39 IEEE Trans. Electron Devices 1444 (1992); C. Mead. "Analog VLSI and Neural Systems" (1989); all of which are hereby incorporated by reference.